1. Field of the Invention
The present invention relates to improved logical circuits having a high speed, current driving capability by the use of CMOS transistors and bipolar transistors.
2. Description of the Prior Art
Conventionally, there were some problems in the logical circuits, such as NAND circuits. FIG. 1 shows a logical circuit consisting of CMOS transistors i.e., two-input NAND circuit, which is comprised of a NAND operational portion 1 and two inverter circuits 3 and 5 connected in series.
The NAND operational portion 1 consists of a pair of P-channel MOS transistor (which is referred to as PMOS transistor hereafter respectively) 7 and N-channel MOS transistors (which is referred to hereafter as NMOS transistor, respectively) 9 and 11, and PMOS transistor 13 and NMOS transistors 15 and 17 which are connected between power supply V.sub.DD and ground and which perform the NAND logical operation of the input signals applied to the input terminals A and B.
The inverter circuit 5 constitutes an output stage of the NAND operational portion 1 and it produces the result of the operation performed in the NAND operational portion 1 from the output terminal C after amplifying it.
When the NAND circuit is constructed only by the CMOS transistors in the manner as described above, it follows that the merits of the CMOS transistors are demonstrated, resulting in the reduction of power consumption. On the other hand, however, since the transfer conductance of the MOS transistor is small, compared with that of the bipolar transistor, the current driving capability or performance becomes small, with the result that a high speed operation is difficult to perform when the load capacity is increased.
In order to overcome the drawback described above, the current driving performance is increased by making the size of the MOS transistors in the output stage large in accordance with the conditions of the load capacity, so as to perform the high speed operation in the NAND circuit according to the prior art. However, here again, this kind of the approach according to the prior art results in a large size of the circuit and this becomes an obstacle, particular in view of realization of less miniaturization in the integrated circuits.
Furthermore, when the NAND circuit is constructed only by the bipolar transistors, the current driving performance can be increased, to be sure. However, a current tends to flow through the circuit even in the steady state, thus increasing the power consumption.
As has been described above, although the power consumption may be reduced in a sense by constructing the logical circuit by the use of only the CMOS transistors, it becomes difficult to obtain a large current driving performance from the miniaturized circuits.
On the other hand, when the logical circuit is constructed only by the bipolar transistors, it results in the increase in the power consumption, i.e., antinomy occurs in this case. As a result, it becomes not possible to increase the current driving performance without making the size of the circuit construction large, while reducing the power consumption.